1. Field of the Invention
The present invention relates to a memory device, and more particularly, to configuring the memory device for a 1-row activation or a 2-row activation.
2. Description of the Related Art
As the storage capacity and operating speed of semiconductor memory devices, such as dynamic random access memories (DRAMs), increase, an increasing number of DRAMs have been developed with hierarchical input/output (I/O) line architectures. These hierarchical I/O lines architectures comprise pairs of local I/O lines and pairs of global I/O lines to quickly drive wordlines and enhance the speed of inputting/outputting data to/from semiconductor memory devices.
FIG. 1 is a diagram of a conventional semiconductor memory device 100 having a 1-row activation configuration. The semiconductor memory device 100 shown in FIG. 1 may be one eighth of a bank of a 512 M DRAM including a plurality of local I/O line pairs LIO11 through LIO15 and LIO21 through LIO25, a plurality of global I/O line pairs GIO<0> through GIO<3> and GIO<4> through GIO<7>, and a plurality of multiplexers LGM1 through LGM8 that connect the local I/O line pairs LIO11 through LIO15 and the global I/O line pairs GIO<0> through GIO<3> and connect the local I/O line pairs LIO21 through LIO25 and the global I/O line pairs GIO<4> through GIO<7>.
Each of the local I/O line pairs LIO11 through LIO15 and LIO21 through LIO25 corresponds to two memory blocks. For example, the local I/O line pair LIO11 corresponds to memory blocks MCB1 and MCB2, and the local I/O line pair LIO22 corresponds to memory blocks MCB3 and MCB4. The local I/O line pairs LIO11 and LIO12 each corresponding to memory blocks MCB1 and MCB2 are separate from the local I/O line pairs LIO21 and LIO22 each corresponding to memory blocks MCB3 and MCB4.
The semiconductor memory device 100 may operate at a X32 double data rate, where 64-bits of data is substantially simultaneously outputted. Since FIG. 1 may show one eighth of a bank of a 512M DRAM, the semiconductor memory device 100 may output 8-bit data at a time.
Each of the global I/O line pairs GIO<0> through GIO<7> may include a global I/O line and an inverted global I/O line to output 1-bit data. Each of the local I/O line pairs LIO11 through LIO15 and LIO21 through LIO25 may include a local I/O line and an inverted local I/O line to transmit 1-bit data.
When a wordline WL, which passes through the memory blocks MCB1 through MCB4, is activated, the multiplexers LGM1 through LGM8 on both sides of the memory blocks MCB1 through MCB4 are activated so that the local I/O line pairs LIO11, LIO12, LIO21, and LIO22 are connected to the global I/O line pairs GIO<0> through GIO<7>. Data may output from the memory blocks MCB1 through MCB4 via the local I/O line pairs LIO11, LIO12, LIO21, and LIO22 and the global I/O line pairs GIO<0> through GIO<7>.
A Joint Electron Device Engineering Council (JEDEC) has recently adopted a 2-row activation configuration as a standard for mobile DRAMs to enhance the speed of writing/reading data to/from a memory by simultaneously activating 2 wordlines. The 2-row activation configuration is a DRAM architecture in which 2 wordlines and a column selection line are simultaneously activated in a data write or read operation. Semiconductor memory devices, however, consume a considerable amount of current when activating 2 wordlines at the same time. To reduce this high current consumption problem, it may be advantageous to incorporate a 1-row activation configuration together with the 2-row activation configuration in a memory device.
The semiconductor memory device 100 has a 1-row activation configuration. Conventionally, semiconductor memory devices having a 1-row activation configuration are separate from semiconductor memory devices having a 2-row activation configuration.
As described above, semiconductor memory devices having a 1-row activation configuration are sometimes more advantageous than semiconductor memory devices having a 2-row activation configuration. Since the JEDEC has adopted a 2-row activation configuration as a standard for mobile DRAMs, however, the need remains for memory devices capable of selecting a 1-row activation configuration or a 2-row activation configuration.